In the prior art, a large number of circuit families such as current switch emitter follower logic (CSEF), transistor-transistor-logic (TTL), diode transistor logic (DTL), Schottky barrier diode transistor logic (STL), and current injection logic also known as merged transistor logic (MTL), are all well known. Each of these circuit families is characterized by certain advantageous features at the expense of various tradeoffs. For example, current switch emitter follower logic is extremely fast but consumes a relatively high amount of power. Similarly, Schottky transistor logic (STL) is relatively high speed with relatively high power consumption. STL further suffers from requiring special processes for fabricating the Schottky barrier diodes. Transistor-transistor logic requires less power per circuit at the expense of somewhat lower switching speeds making it particularly advantageous for smaller electronic computing systems. Merged transistor logic has the virtue of very high packing density, lower power consumption/dissipation, and a relatively large fan-out/fan-in logic capability. As a tradeoff, merged transistor logic is characterized by relatively low switching speed (even lower than transistor-transistor logic) due to the requirement of an inversely operated NPN transistor structure and the increased carrier storage resulting from the high saturation of the switched-on NPN transistor. Merged transistor logic is also relatively sensitive to crystalline imperfections such as pipe problems found in integrated circuit structures.
It is thus apparent that there is no single circuit family that provides an ideal solution to every application, but rather various tradeoffs must always be considered. As will become more apparent from the following and more detailed description of my invention, the advantageous aspects of merged transistor logic are retained while further improving performance and fabrication reliability previously associated with higher performance logic circuits such as Schottky barrier diode transistor logic.